The invention lies in the field of semiconductor manufacture. More specifically, the invention relates to a process for fabricating a buried, laterally insulated zone of increased conductivity in a semiconductor substrate. The invention relates, in particular, to a process for fabricating a buried, laterally insulated zone of increased conductivity in a semiconductor substrate by means of deep trench insulation.
Buried zones of increased conductivity, so-called xe2x80x9cburied layers,xe2x80x9d are used in a large number of components appertaining to semiconductor technology in order to enable lateral contact to be made with the components. Thus, in radio-frequency technology, for example, the xe2x80x9cburied layerxe2x80x9d is part of the collector in a vertical bipolar transistor.
In order that neighboring components on a chip do not interfere with one another""s operation, it is necessary for the components to be insulated from one another by insulation structures. If two neighboring components each have a xe2x80x9cburied layer,xe2x80x9d then those xe2x80x9cburied layersxe2x80x9d must also be insulated from one another.
The simplest option for insulation of this type consists in leaving sufficient space between the individual zones of increased conductivity, so that the individual zones are insulated from one another by the substrate. In addition, a further implantation (xe2x80x9cchannel stopperxe2x80x9d) is inserted between the individual zones of increased conductivity, which further implantation produces a blocking PN junction.
However, this option has the disadvantage that the packing density of the component is severely limited as a result. Furthermore, it has been found that in applications in radio-frequency technology, the cut-off frequency of the bipolar transistors which can be achieved is limited by the capacitance which forms between the zone of increased conductivity and the substrate. In order to be able to achieve cut-off frequencies of greater than 50 GHz, this zone-substrate capacitance must be significantly reduced.
In order to solve this problem, deep oxide-filled trenches (xe2x80x9cdeep trenchesxe2x80x9d) have been proposed which completely surround each zone of increased conductivity in the form of a closed ring. However, a series of difficulties arise particularly in the course of planarizing the oxide-filled trenches. Large topological differences are produced on the surface of the semiconductor wafer as a result of the filling of the trenches. Those differences can have a disruptive effect on subsequent process steps. The consequence of this is that the topological differences have to be removed again by means of planarization, for example etching back. However, planarization by etching back requires complex and expensive process control particularly when LOCOS insulation is simultaneously used on the substrate surface.
It is accordingly an object of the invention to provide a novel process for fabricating a buried, laterally insulated zone of increased conductivity in a semiconductor substrate, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which operates economically with little outlay in terms of time and cost and which enables a patterned substrate having optimum planarity.
With the foregoing and other objects in view there is provided, in accordance with the invention, a process for fabricating a buried, laterally insulated zone of increased conductivity in a semiconductor substrate, having the following steps:
providing a substrate with a buried zone of increased conductivity;
forming a reference layer on the substrate;
patterning the reference layer;
forming a trench in the substrate; and
filling the trench with insulation material and depositing the insulation material on the structure thus produced;
selecting a material of the reference layer such that a growth rate of the insulation material on the reference layer is at least by a factor of two less than a growth rate of the insulation material on a surface of the trench to be covered.
The trench surface to be covered will usually be composed of substrate material. However, intermediate layers may also be provided.
The buried, laterally insulated zones of increased conductivity produced by the process according to the invention can be packed more densely, as a result of which it is possible to produce a higher integration level on the semiconductor wafers. Furthermore, the capacitance formed between the zones of increased conductivity and the substrate is significantly reduced, as a result of which it is possible to obtain higher cut-off frequencies in radio-frequency technology. The process according to the invention enables the zones of increased conductivity to be insulated without large topological differences being built up on the surface of the substrate.
In accordance with an added feature of the invention, the substrate is a silicon substrate and the insulation material for filling the trench is silicon oxide.
In accordance with an additional feature of the invention, the reference layer is silicon nitride layer, a titanium nitride layer, or a polysilicon layer. If the reference layer is polysilicon, it is in particular a doped polysilicon layer. The silicon oxide is advantageously deposited in an ozone-activated CVD process, in particular SACVD process. Such ozone-activated CVD processes are described in detail in the European specifications EP 0 582 724 A1 and EP 0 537 001 A1, for example. In particular an SACVD deposition process is distinguished by very good filling properties, which means that even trenches having a large aspect ratio of greater than 2:1 can be filled without the formation of shrink holes.
In accordance with a further feature of the invention, the filling/depositing step is continued until a substantially planar surface is formed in the surroundings of the trench.
The reference layer can be applied directly to the substrate surface. Alternatively, however, in accordance with again an added feature of the invention, at least one intermediate layer is formed between the substrate and the reference layer. In a preferred embodiment, the intermediate layer is an oxide layer (LOCOS oxide, pad oxide).
In accordance with again an additional feature of the invention, thermal oxidation is carried out subsequently to the filling and depositing steps. The thermal oxidation may be at 900-1000xc2x0 C. for 10-30 minutes. The oxidation acts through the material already deposited, in particular through the silicon oxide already deposited, and reduces damage which has remained in the substrate and may have occured during the production of the trench.
In the alternative, a liner oxidation process is carried out subsequently to the step of forming the trench. Damage in the substrate can also be reduced by the liner oxidation. However, the oxide which has grown on must subsequently be removed by wet-chemical means since otherwise the selectivity of the subsequent deposition process is not provided. This xe2x80x9csacrificial oxidexe2x80x9d removes for example etching damage and stationary charges at the edge of the trench, which would impair the insulation properties of the trench.
In accordance with again another feature of the invention, the insulation material is removed from above a level of the reference layer after the filling and depositing step. A wet-chemical or plasma-chemical process is advantageously used for this purpose.
In accordance with again a further feature of the invention, the zone of increased conductivity is located at a given depth in the substrate, and wherein the trench is formed into the substrate to a depth below the zone of increased conductivity.
In accordance with yet another feature of the invention, the trench is an annular trench disposed laterally of and completely enclosing at least a part of the zone of increased conductivity.
Usually, the individual components are additionally insulated from one another on the substrate surface by means of a field oxide, in particular a LOCOS oxide. Therefore, it is particularly preferred if the trench has at least one shallow region and at least one deep region. In this way, the shallow region of the trench can replace the field oxide on the substrate surface and a well-planarized substrate surface is obtained.
In accordance with a concomitant feature of the invention, the insulation material is removed from above a level of the reference layer by a CMP process. Since, in the case of using the shallow trenches, the wafer surface is already essentially planar before a subsequent CMP step, no appreciable xe2x80x9cdishingxe2x80x9d occurs during a CMP step even in the case of large trench regions.
In accordance with yet again a further feature of the invention, a ratio of a width of the deep region to a step height of the shallow region is approximately equal to 2*xcex1/(xcex1xe2x88x921), where xcex1 corresponds to a ratio of the growth rate of the insulation material on the surface of the trench to be covered to the growth rate of the insulation material on the reference layer. As a result, the two regions of the trench can be filled in a simple manner such that a planar surface of the deposited insulation material is produced.
Although the invention is illustrated and described herein as embodied in process for fabricating a buried, laterally insulated zone of increased conductivity in a semiconductor substrate, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.